About HDLRuby

HDLRuby is a library for describing and simulating digital electronic systems.

Note:

If you are new to HDLRuby, it is recommended that you consult first the following tutorial (even if you are a hardware person):

And if you want an html version the following command with create a tuto folder containing all the required files, then just open tuto/tutorial_sw.html:

hdrcc --get-tuto

What’s new

For HDLRuby version 3.3.0:

For HDLRuby version 3.2.0:

For HDLRuby version 3.1.0:

For HDLRuby version 3.0.0:

Install:

The recommended installation method is from rubygems as follows:

gem install HDLRuby

Developers willing to contribute to HDLRuby can install the sources from GitHub as follows:

git clone https://github.com/civol/HDLRuby.git

Warning:

Compiling HDLRuby descriptions

Using the HDLRuby compiler

‘hdrcc’ is the HDLRuby compiler. It takes as input an HDLRuby file, checks it, and can produce as output a Verilog HDL, VHDL, or a YAML low-level description of HW components but it can also simulate the input description.

Usage:

hdrcc [options] <input file> <output directory>

Where:

Options
-I, --interactive Run in interactive mode
-y, --yaml Output in YAML format
-v, --verilog Output in Verilog HDL format
-V, --vhdl Output in VHDL format
-s, --syntax Output the Ruby syntax tree
-C, --clang Output the C code of the standalone simulator
-S, --sim Perform the simulation with the default engine
--csim Perform the simulation with the standalone engine
--rsim Perform the simulation with the Ruby engine
--rcsim Perform the simulation with the Hybrid engine
--vcd Make the simulator generate a VCD file
-d, --directory Specify the base directory for loading the HDLRuby files
-D, --debug Set the HDLRuby debug mode
-t, --top system Specify the top system describing the circuit to compile
-p, --param x,y,z Specify the generic parameters
--get-samples Copy the sample directory (hdr_samples) to current one, then exit
--version Show the version number, then exit
-h, --help Show the help message

Notes:

Examples:

hdrcc --yaml --top adder adder.rb adder
hdrcc -v adder.rb adder
hdrcc -V -t adder --param 16 adder_gen.rb adder
hdrcc -y -t multer -p 16,16,32 multer_gen.rb multer
hdrcc -S counter_bench.rb counter

As a policy, the default simulation engine is set to the fastest one (currently it is the hybrid engine).

hdrcc -I
hdrcc -I pry

Using HDLRuby in interactive mode

When running in interactive mode, the HDLRuby framework starts a REPL prompt and creates a working directory called HDLRubyWorkspace. By default, the REPL is irb, but it can be set to pry. Within this prompt, HDLRuby code can be written like in an HDLRuby description file. However, to process this code the following commands are added:

hdr_make(<module>)
hdr_yaml
hdr_hdr
hdr_verilog
hdr_vhdl
hdr_sim

HDLRuby programming guide

HDLRuby has been designed to bring the high flexibility of the Ruby language to hardware descriptions while ensuring that they remain synthesizable. In this context, all the abstractions provided by HDLRuby are in the way of describing hardware, but not in its execution model, this latter being RTL by construction.

The second specificity of HDLRuby is that it supports natively all the features of the Ruby language.

Notes:

Introduction

This introduction gives a glimpse of the possibilities of the language. However, we do recommend consulting the section about the high-level programming features to have a more complete view of the advanced possibilities of this language.

At first glance, HDLRuby appears like any other HDL (like Verilog HDL or VHDL), for instance, the following code describes a simple D-FF:

system  do
   bit.input , , 
   bit.output 

   par(clk.posedge) do
      q <= d & ~rst
   end
end

As can be seen in the code above, system is the keyword used for describing a digital circuit. This keyword is the equivalent of the Verilog HDL module. In such a system, signals are declared using a <type>.<direction> construct where type is the data type of the signal (e.g., bit as in the code above) and direction indicates if the signal is an input, an output, an inout or an inner one; and executable blocks (similar to always block of Verilog HDL) are described using the par keyword when they are parallel and seq when they are sequential (i.e., with respectively non-blocking and blocking assignments).

After such a system has been defined, it can be instantiated. For example, a single instance of the dff system named dff0 can be declared as follows:

dff

The ports of this instance can then be accessed to be used like any other signals, e.g., dff0.d for accessing the d input of the FF.

Several instances can also be declared in a single statement. For example, a 2-bit counter based on the previous dff circuits can be described as follows:

system  do
   input ,
   output 

   dff [ ,  ]

   dff0.clk <= clk
   dff0.rst <= rst
   dff0.d   <= ~dff0.q

   dff1.clk <= ~dff0.q 
   dff1.rst <= rst
   dff1.d   <= ~dff1.q

   q <= dff1.q
end

The instances can also be connected while being declared. For example, the code above can be rewritten as follows:

system  do
   input , 
   output 

   dff().(clk, rst, ~dff0.q)
   dff().(~dff0.q, rst, ~dff1.q, q)
end

In the code above, two possible connection methods are shown: for dff0 ports are connected by name, and for dff1 ports are connected in declaration order. Please notice that it is also possible to connect only a subset of the ports while declaring, as well as to reconnect already connected ports in further statements.

While a circuit can be generated from the code given above, a benchmark must be provided to test it. Such a benchmark is described by constructs called timed behavior that give the evolution of signals depending on the time. For example, the following code simulates the previous D-FF for 4 cycles of 20ns each, with a reset on the first cycle, set of signal d to 1 for the third cycle and set this signal to 0 for the last.

system  do
   
   dff 

   timed do
      dff0.clk <= 0
      dff0.rst <= 1
      !10.ns
      dff0.clk <= 1
      !10.ns
      dff0.clk <= 0
      dff0.rst <= 0
      dff0.d   <= 1
      !10.ns
      dff0.clk <= 1
      !10.ns
      dff0.clk <= 0
      !10.ns
      dff0.clk <= 1
      !10.ns
      dff0.clk <= 0
      dff0.d   <= 1
      !10.ns
      dff0.clk <= 1
      !10.ns
   end
end

The code describing a dff given above is not much different from its equivalent in any other HDL. However, HDLRuby provides several features for achieving higher productivity when describing hardware. We will now describe a few of them.

First, several syntactic sugars exist that allow shorter code, for instance, the following code is strictly equivalent to the previous description of dff:

system  do
   input , , 
   output 

   (q <= d & ~rst).at(clk.posedge)
end

Then, it often happens that a system will end up with only one instance. In such a case, the system declaration can be omitted, and an instance can be directly declared as follows:

instance  do
   input , , 
   output 

   (q <= d & ~rst).at(clk.posedge)
end

In the example above, dff_single is an instance describing, again, a D-FF, but whose system is anonymous.

Furthermore, generic parameters can be used for anything in HDLRuby. For instance, the following code describes an 8-bit register without any parameterization:

system  do
   input , 
   [7..0].input 
   [7..0].output 

   (q <= d & [~rst]*8).at(clk.posedge)
end

But it is also possible to describe a register of arbitrary size as follows, where n is the parameter giving the number of bits of the register:

system  do |n|
   input , 
   [n-1..0].input 
   [n-1..0].output 

   (q <= d & [~rst]*n).at(clk.posedge)
end

Or, even further, it is possible to describe a register of arbitrary type (not only bit vectors) as follows:

system  do |typ|
   input , 
   typ.input 
   typ.output 

   (q <= d & [~rst]*typ.width).at(clk.posedge)
end

Wait… I have just realized that D-FF without any inverted output does not look very serious. So, let us extend the existing dff to provide an inverted output. There are three ways to do this. First, inheritance can be used: a new system is built inheriting from dff as it is done in the following code.

system , dff do
   output 
   qb <= ~q
end

The second possibility is to modify dff afterward. In HDLRuby, this is achieved using the open method as it is done in the following code:

dff.open do
   output 
   qb <= ~q
end

The third possibility is to modify directly a single instance of dff which requires an inverted output, using again the open method, as in the following code:

# Declare dff0 as an instance of dff
dff 

# Modify it
dff0.open do
   output 
   qb <= ~q
end

In this latter case, only dff0 will have an inverted output, the other instances of dff will not change.

Now assuming we opted for the first solution, we have now dff_full, a highly advanced D-FF with such unique features as an inverted output. So, we would like to use it in other designs, for example, a shift register of n bits. Such a system will include a generic number of dff_full instances and can be described as follows making use of the native Ruby method each_cons for connecting them:

system  do |n|
   input , 
   input 
   output , 

   # Instantiating n D-FF
   [n].dff_full 
   
   # Connect the clock and the reset.
   dffIs.each { |ff| ff.clk <= clk ; ff.rst <= rst }

   # Interconnect them as a shift register
   dffIs[0..-1].each_cons(2) { |ff0,ff1| ff1.d <= ff0.q }

   # Connects the input and output of the circuit
   dffIs[0].d <= i0
   o0 <= dffIs[-1].q
   o0b <= dffIs[-1].qb
end

As can be seen in the above examples, in HDLRuby, any construct is an object and therefore includes methods. For instance, declaring a signal of a given type and direction (input, output, or inout) is done as follows so that direction is a method of the type, and the signal names are the arguments of this method (symbols or string are supported.)

<type>.<direction> <list of symbols representing the signal>

Of course, if you do not need to use the specific component dff_full you can describe a shift register more simply as follows:

system  do |n|
   input , 
   input 
   output 
   [n].inner 
   
   par (clk.posedge) do
      hif(rst) { sh <= 0 }
      helse { sh <= [sh[n-2..0], i0] }
   end
   
   o0 <= sh[n-1]
end

Now, let us assume you want to design a circuit that performs a sum of products of several inputs with constant coefficients. For the case of 4 16-bit signed inputs and given coefficients as 3, 4, 5, and 6. The corresponding basic code could be as follows:

system  do
   signed[16].input , , , 
   signed[16].output 
   
   o <= i0*3 + i1*4 + i2*5 + i3*6
end

The description above is straightforward, but it would be necessary to rewrite it if another circuit with different bit widths or coefficients is to be designed. Moreover, if the number of coefficients is large an error in the expression will be easy to make and hard to find. A better approach would be to use a generic description of such a circuit as follows:

system  do |typ,coefs|
   typ[coefs.size].input 
   typ.output 
   
   o <= coefs.each_with_index.reduce(_b0) do |sum,(coef,i)|
      sum + ins[i]*coef
   end
end

In the code above, there are two generic parameters, typ, which indicates the data type of the circuit, and coefs, which is assumed to be an array of coefficients. Since the number of inputs depends on the number of provided coefficients, it is declared as an array of width bit signed whose size is equal to the number of coefficients.

The description of the sum of products may be more difficult to understand for people not familiar with the Ruby language. The each_with_index method iterates over the coefficients adding their index as an iteration variable, the resulting operation (i.e., the iteration loop) is then modified by the reduce method that accumulates the code passed as arguments. This code, starting by |sum,coef,i| performs the addition of the current accumulation result (sum) with the product of the current coefficient (coef) and input (ins[i], where i is the index) in the iteration. The argument _b0 initializes the sum to 0.

While slightly longer than the previous description, this description allows declaring a circuit implementing a sum of products with any bit width and any number of coefficients. For instance, the following code describes a signed 32-bit sum of products with 16 coefficients (just random numbers here).

sumprod(signed[32], [3,78,43,246, 3,67,1,8, 47,82,99,13, 5,77,2,4]).()

As seen in the code above, when passing a generic argument for instantiating a generic system, the name of the instance is put between brackets to avoid confusion.

While the description sumprod is already usable in a wide range of cases, it still uses standard addition and multiplication. However, there are cases where specific components are to be used for these operations, either for the sake of performance, compliance with constraints, or because functionally different operations are required (e.g., saturated computations). This can be solved by using functions implementing such computation in place of operators, for example, as follows:

system  do |typ,coefs|
   typ[coefs.size].input ins
   typ.output 
   
   o <= coefs.each_with_index.reduce(_b0) do 
   |sum,(coef,i)|
      add(sum, mult(ins[i]*coef))
   end
end

Where add and mult are functions implementing the required specific operations. HDLRuby functions are equivalent to the Verilog HDL ones. In our example, an addition that saturates at 1000 could be described as follows:

hdef  do |x,y|
   inner 
   seq do
      res <= x + y
      (res <= 1000).hif(res > 1000)
   end
end

With HDLRuby functions, the result of the last statement in the return value, in this case, that will be the value of res. The code above is also an example of the usage of the postfixed if statement, it is an equivalent of the following code:

      hif(res>1000) { res <= 1000 }

With functions, it is enough to change their content to obtain a new kind of circuit without changing the main code. This approach suffers from two drawbacks though: first, the level of saturation is hard coded in the function, and second, it would be preferable to be able to select the function to execute instead of modifying its code. For the first problem, a simple approach is to add an argument to the function given the saturation level. Such an add function would therefore be as follows:

hdef  do |max, x, y|
   inner 
   seq do
      res <= x + y
      (res <= max).hif(res > max)
   end
end

It would however be necessary to add this argument when invoking the function, e.g., add(1000,sum,mult(...)). While this argument is relevant for addition with saturation, it is not for the other kinds of addition operations, and hence, the code of sumprod has no general purpose.

HDLRuby provides two ways to address such issues. First, it is possible to pass code as an argument. In the case of sumprod, it would then be enough to add two arguments that perform the required addition and multiplication. The example is below:

system  do |add,mult,typ,coefs|
   typ[coefs.size].input ins
   typ.output 
   
   o <= coefs.each_with_index.reduce(_b0) do 
   |sum,(coef,i)|
      add.(sum, mult.(ins[i]*coef))
   end
end

Note:

Assuming the addition with saturation is now implemented by a function named add_sat and a multiplication with saturation is implemented by a function named mult_sat (with similar arguments), a circuit implementing a signed 16-bit sum of product saturating at 1000 with 16 coefficients could be described as follows:

sumprod_proc( 
        proc { |x,y| add_sat(1000,x,y) },
        proc { |x,y| mult_sat(1000,x,y) },
        signed[64], 
        [3,78,43,246, 3,67,1,8,
         47,82,99,13, 5,77,2,4]).()

As seen in the example above, a piece of code is passed as an argument using the proc keyword.

A second possible approach provided by HDLRuby is to declare a new data type with redefined addition and multiplication operators. For the case of a 16-bit saturated addition and multiplication the following generic data type can be defined (for signed computations):

signed[16].typedef(:sat16_1000)

sat16_1000.define_operator(:+) do |x,y|
      tmp = x + y
      mux(tmp > 1000,tmp,1000)
   end
end

In the code above, the first line defines the new type sat16_1000 to be 16-bit signed, and the remaining overloads (redefines) the + operator for this type (the same should be done for the * operator). Then, the initial version of sumprod can be used with this type to achieve saturated computations as follows:

sumprod(sat16_1000, 
        [3,78,43,246, 3,67,1,8,
        47,82,99,13, 5,77,2,4]).()

It is also possible to declare a generic type. For instance, a generic signed type with saturation can be declared as follows:

typedef  do |width, max|
   signed[width]
end


sat.define_operator(:+) do |width,max, x,y|
      tmp = x + y
      mux(tmp > max, tmp, max)
   end
end

Note:

With this generic type, the circuit can be declared as follows:

sumprod(sat(16,1000), 
        [3,78,43,246, 3,67,1,8,
         47,82,99,13, 5,77,2,4]).()

Lastly note, HDLRuby is also a language with supports reflection for all its constructs. For example, the system of an instance can be accessed using the systemT method, and this latter can be used to create other instances. For example, previously, dff_single was declared with an anonymous system (i.e., it cannot be accessed by name). This system can however be used as follows to generate another instance:

dff_single.systemT.instantiate()

In the above example, dff_not_single is declared to be an instance of the same system as dff_single.

This reflection capability can also be used for instance, for accessing the data type of a signal (sig.type), but also the current basic block (cur_block), the current process (cur_behavior), and so on. The standard library of HDLRuby includes several hardware constructs like finite state machine descriptors and is mainly based on using these reflection features.

How does HDLRuby work

Contrary to descriptions in high-level HDL like SystemVerilog, VHDL, or SystemC, HDLRuby descriptions are not software-like descriptions of hardware but are programs meant to produce hardware descriptions. In other words, while the execution of a common HDL code will result in some simulation of the described hardware, the execution of HDLRuby code will result in some low-level hardware description. This low-level description is synthesizable and can also be simulated like any standard hardware description. This decoupling of the representation of the hardware from the point of view of the user (HDLRuby), and the actual hardware description (HDLRuby::Low) makes it possible to provide the user with any advanced software features without jeopardizing the synthesizability of the actual hardware description.

For that purpose, each construct in HDLRuby is not a direct description of some hardware construct, but a program that generates the corresponding description. For example, let us consider the following line of code of HDLRuby describing the connection between signal a and signal b:

   a <= b

Its execution will produce the actual hardware description of this connection as an object of the HDLRuby::Low library — in this case, an instance of the HDLRuby::Low::Connection class. Concretely, an HDLRuby system is described by a Ruby block, and the instantiation of this system is performed by executing this block. The actual synthesizable description of this hardware is the execution result of this instantiation.

From there, we will describe in more detail each construct of HDLRuby.

Naming rules

Several constructs in HDLRuby are referred to by name, e.g., systems and signals. When such constructs are declared, their names are to be specified by Ruby symbols starting with a lowercase. For example, :hello is a valid name declaration, but :Hello is not.

After being declared, the construct can be referred to by using the name directly (i.e., without the : of Ruby symbols). For example, if a construct has been declared with :hello as the name, it will be afterward referred to by hello.

Systems and Signals

A system represents a digital system and corresponds to a Verilog HDL module. A system has an interface comprising input, output, and inout signals, and includes structural and behavioral descriptions.

A signal represents a state in a system. It has a data type and a value, the latter varying with time. HDLRuby signals can be viewed as abstractions of both wires and registers in a digital circuit. As a general rule, a signal whose value is explicitly set all the time models a wire, otherwise it models a register.

Declaring an empty system

A system is declared using the keyword system. It must be given a Ruby symbol for its name and a block that describes its content. For instance, the following code describes an empty system named box:

system() {}

Notes:

system  does
end

Declaring a system with an interface

The interface of a system can be described anywhere in its body, but it is recommended to do it at its beginning. This is done by declaring input, output, or inout signals of given data types as follows:

<data type>.<direction> <list of colon-preceded names>

For example, declaring a 1-bit input signal named clk can be declared as follows:

bit.input

Now, since bit is the default data type in HDLRuby, it can be omitted as follows:

input

The following is a more complete example: it is the code of a system describing an 8-bit data, 16-bit address memory whose interface includes a 1-bit input clock (clk), a 1-bit signal for selecting reading or writing access (rwb), a 16-bit address input (addr), and an 8-bit data inout — the remaining of the code describes the content and the behavior of the memory.

system  do
    input , 
    [15..0].input 
    [7..0].inout 

    bit[7..0][2**16].inner 
    
    par(clk.posedge) do
        hif(rwb) { data <= content[addr] }
        helse    { content[addr] <= data }
    end
end

Structural description in a system

In a system, structural descriptions consist of subsystems and interconnections among them.

A subsystem is obtained by instantiating an existing system as follows, where <system name> is the name of the system to instantiate (without any colon):

<system name> :<instance name>

For example, system mem8_16 declared in the previous section can be instantiated as follows:

mem8_16

It is also possible to declare multiple instances of the same system at a time as follows:

<system name> [list of colon-separated instance names]

For example, the following code declares two instances of system mem8_16:

mem8_16 [ ,  ]

Interconnecting instances may require internal signals in the system. Such signals are declared using the inner direction. For example, the following code declares a 1-bit inner signal named w1 and a 2-bit inner signal named w2:

inner 
[1..0].inner

If the signal is not meant to be changed, it can be declared using the constant keyword instead of inner.

A connection between signals is done using the arrow operator <= as follows:

<destination> <= <source>

The <destination> must be a reference to a signal, and the <source> can be any expression.

For example, the following code connects signal w1 to signal ready and signal clk to the first bit of signal w2:

ready <= w1
w2[0] <= clk

As another example, the following code connects to the second bit of w2 the output of an AND operation between clk and rst as follows:

w2[1] <= clk & rst

The signals of an instance can be connected through the arrow operator too, provided they are properly referred to. One way to refer to them is to use the dot operator . on the instance as follows:

<instance name>.<signal name>

For example, the following code connects signal clk of instance mem8_16I to signal clk of the current system:

mem8_16I.clk <= clk

It is also possible to connect multiple signals of an instance using the call operator .() as follows, where each target can be any expression:

<instance name>.(<signal name0>: <target0>, ...)

For example, the following code connects signals clk and rst of instance mem8_16I to signals clk and rst of the current system. As seen in this example, this method allows partial connection since the address and the data buses are not connected yet.

mem8_16I.(clk, rst)

This last connection method can be used directly while declaring an instance. For example, mem8_16I could have been declared and connected to clk and rst as follows:

mem8_16().(clk, rest)

To summarize this section, here is a structural description of a 16-bit memory made of two 8-bit memories (or equivalent) sharing the same address bus, and using respectively the lower and the higher 8-bits of the data bus:

system  do
   input , 
   [15..0].input 
   [15..0].inout 

   mem8_16().(clk, rwb, addr, data[7..0])
   mem8_16().(clk, rwb, addr, data[15..8])
end

And here is an equivalent code using the arrow operator:

system  do
   input , 
   [15..0].input 
   [15..0].inout 

   mem8_16 [, ]

   memL.clk  <= clk
   memL.rwb  <= rwb
   memL.addr <= addr
   memL.data <= data[7..0]

   memH.clk  <= clk
   memH.rwb  <= rwb
   memH.addr <= addr
   memH.data <= data[15..8]
end

Initialization of signals

Output, inner, and constant signals of a system can be initialized when declared using the following syntax in place of the usual name of the signal:

<signal name>: <intial value>

For example, a single-bit inner signal named sig can be initialized to 0 as follows:

inner 0

As another example, an 8-bit 8-word ROM could be declared and initialized as follows:

bit[8][-8] [ 0,1,2,3,4,5,6,7 ]

Scope in a system

General scopes

The signals of the interface of signals are accessible from anywhere in an HDLRuby description. This is not the case for inner signals and instances: they are accessible only within the scope they are declared in.

A scope is a region of the code where locally declared objects are accessible. Each system has its scope that cannot be accessible from another part of an HDLRuby description. For example, in the following code signals d and qb as well as instance dffI cannot be accessed from outside system div2:

system  do
   input 
   output 
   
   inner , 
   d <= qb
   
   dff_full().(clk, d, q, qb)

For robustness or, readability purposes, it is possible to add an inner scope inside the existing scope using the sub keyword as follows:

sub do
   <code>
end

For example, in the code below signal sig is not accessible from outside the additional inner scope of system sys

system  do
   ...
   sub
      inner 
      <sig is accessible here>
   end
   <sig is not accessible from here>
end

It is also possible to add an inner scope within another inner scope as follows:

system  do
   ...
   sub
      inner 
      <sig0 is accessible here>
      sub
         inner 
         <sig0 and sig1 are accessible here>
      end
      <sig1 is not accessible here>
   end
   <neither sig0 nor sig1 are accessible here>
end

Within the same scope, it is not possible to declare multiple signals or instances with the same name. However, it is possible to declare a signal or an instance with a name identical to one previously declared outside the scope: the inner-most declaration will be used.

Named scopes

It is possible to declare a scope with a name as follows:

sub :<name> do
   <code>
end

Where:

Contrary to the case of scopes without a name, signals, and instances declared within a named scope can be accessed outside using this name as a reference. For example, in the code below signal sig declared within scope named scop is accessed outside it using scop.sig:

sub  do
   inner 
   ...
end
...
scop.sig <= ...

Behavioral description in a system.

In a system, parallel behavioral descriptions are declared using the par keyword, and sequential behavioral descriptions are declared using the seq keyword. They are the equivalent of the Verilog HDL always blocks.

A behavior is made of a list of events (the sensitivity list) upon which it is activated, and a list of statements. A behavior is declared as follows:

par <list of events> do
   <list of statements>
end

In addition, it is possible to declare inner signals within an execution block. While such signals will be physically linked to the system, they are only accessible within the block they are declared into. This permits a tighter scope for signals, which improves the readability of the code and makes it possible to declare several signals with identical names provided their respective scopes are different.

An event represents a specific change in the state of a signal. For example, a rising edge of a clock signal named clk will be represented by the event clk.posedge. In HDLRuby, events are obtained directly from expressions using the following methods: posedge for a rising edge, negedge for a falling edge, and edge for any edge. Events are described in more detail in section Events.

When one of the events of the sensitivity list of a behavior occurs, the behavior is executed, i.e., each of its statements is executed in sequence. A statement can represent a data transmission to a signal, a control flow, a nested execution block, or the declaration of an inner signal (as stated earlier). Statements are described in more detail in section statements. In this section, we focus on the transmission statements and the block statements.

A transmission statement is declared using the arrow operator <= as follows:

<destination> <= <source>

The <destination> must be a reference to a signal, and the <source> can be any expression. A transmission has therefore the same structure as a connection. However, its execution model is different: whereas a connection is continuously executed, a transmission is only executed during the execution of its block.

A block comprises a list of statements. It is used for adding hierarchy to a behavior. Blocks can be either parallel or sequential, i.e., their transmission statements are respectively non-blocking or blocking. By default, a top block is created when declaring a behavior, and it inherits from its execution mode. For example, with the following code, the top block of the behavior is sequential.

system  do
   seq do
      <list of statements>
   end
end

It is possible to declare new blocks within an existing block. For declaring a sub-block with the same execution mode as the upper one, the keyword sub is used. For example, the following code declares a sub-block within a sequential block, with the same execution mode:

system  do
   seq do
      <list of statements>
      sub do
         <list of statements>
      end
   end
end

A sub-block can also have a different execution mode if it is declared using seq, which will force sequential execution mode, and par which will force parallel execution mode. For example, in the following code a parallel sub-block is declared within a sequential one:

system  do
   seq do
      <list of statements>
      par do
         <list of statements>
      end
   end
end

Sunblocks have their scope so that it is possible to declare signals without colliding with existing ones. For example, it is possible to declare three different inner signals all called sig as follows:

...
par(<sensibility list>) do
   inner 
   ...
   sub do
      inner 
      ...
      sub do
         inner 
         ...
      end
   end
   ...
end

To summarize this section, here is a behavioral description of a 16-bit shift register with asynchronous reset (hif and helse are keywords used for specifying hardware if and else control statements).

system  do
   input , , 
   output 

   [15..0].inner 

   dout <= reg[15] # The output is the last bit of the register.

   par(clk.posedge) do
      hif(rst) { reg <= 0 }
      helse do
         reg[0] <= din
         reg[15..1] <= reg[14..0]
      end
   end
end

In the example above, the order of the transmission statements is of no consequence. This is not the case for the following example, which implements the same register using a sequential block. In this second example, putting the statement reg[0] <= din in the last place would have led to an invalid functionality for a shift register.

system  do
   input , , 
   output 

   [15..0].inner 

   dout <= reg[15] # The output is the last bit of the register.

   par(clk.posedge) do
      hif(rst) { reg <= 0 }
      helse seq do
         reg[0] <= din
         reg <= reg[14..0]
      end
   end
end

Note:

Extra features for the description of behaviors

Single-statement behaviors

It often happens that a behavior contains only one statement. In such a case, the description can be shortened using the at operator as follows:

( statement ).at(<list of events>)

For example, the following two code samples are equivalent:

par(clk.posedge) do
   a <= b+1
end
( a <= b+1 ).at(clk.posedge)

For the sake of consistency, this operator can also be applied to block statements as follows, but it is probably less readable than the standard declaration of behaviors:

( seq do
     a <= b+1
     c <= d+2
  end ).at(clk.posedge)

Insertion of statements at the beginning of a block

By default, the statements of a block are added in order of appearance in the code. However, it is also possible to insert statements at the top of the current block using the unshift command within a block as follows:

unshift do
   <list of statements>
end

For example, the following code inserts two statements at the beginning of the current block:

par do
   x <= y + z
   unshift do
      a <= b - c
      u <= v & w
    end
end

The code above will result in the following block:

par do
   a <= b - c
   u <= v & w
   x <= y + z
end

Note: - While of no practical use for simple circuit descriptions, this feature can be used in advanced generic component descriptions.

Reconfiguration

In HDLRuby, dynamically reconfigurable devices are modeled by instances having more than one system. Adding systems to an instance is done as follows:

<instance>.choice(<list of named systems>)

For example, assuming systems sys0, sys1, and sys2 have been previously declared a device named dev012 able to be reconfigured to one of these three systems would be declared as follows (the connections of the instance, omitted in the example, can be done as usual):

sys0  # dev012 is at first a standard instance of sys0
dev012.choice(sys1, sys2) # Now dev012 is reconfigurable

After the code above, instance dev012 can be dynamically reconfigured to sys0, sys1, and sys2 with respective names dev012, conf1, and conf2.

Note: The name of the initial system in the reconfigurations is set to be the name of the instance.

A reconfigurable instance can then be reconfigured using the command configure as follows:

<instance>.configure(<name or index>)

In the code above, the argument of configure can either be the name of the configuration as previously declared with choice, or its index in order of declaration. For example in the following code, instance dev012 is reconfigured to system sys1, then system sys0 the system sys2:

dev012.configure()
!1000.ns
dev012.configure()
!1000.ns
dev012.configure(2)

These reconfiguration commands are treated as regular RTL statements in HDLRuby and are supported by the simulator. However, in the current version of the HDLRuby, these statements are ignored when generating Verilog HDL or VHDL code.

Events

Each behavior of a system is associated with a list of events, called a sensitivity list, that specifies when the behavior is to be executed. An event is associated with a signal and represents the instant when the signal reaches a given state.

There are three kinds of events: positive edge events represent the instants when their corresponding signals vary from 0 to 1, and negative edge events represent the instants when their corresponding signals vary from 1 to 0 and the change events represent the instants when their corresponding signals vary. Events are declared directly from the signals, using the posedge operator for a positive edge, the negedge operator for a negative edge, and the change operator for change. For example, the following code declares 3 behaviors activated respectively on the positive edge, the negative edge, and any change of the clk signal.

inner 

par(clk.posedge) do
...
end

par(clk.negedge) do
...
end

par(clk.change) do
...
end

Note: - The change keyword can be omitted.

Statements

Statements are the basic elements of a behavioral description. They are regrouped in blocks that specify their execution mode (parallel or sequential). There are four kinds of statements: the transmit statement which computes expressions and sends the result to the target signals, the control statement which changes the execution flow of the behavior, the block statement (described earlier), and the inner signal declaration.

Note:

Transmit statement

A transmit statement is declared using the arrow operator <= within a behavior. Its right value is the expression to compute and its left value is a reference to the target signals (or parts of signals), i.e., the signals (or parts of signals) that receive the computation result.

For example, the following code transmits the value 3 to signal s0 and the sum of the values of signals i0 and i1 to the first four bits of signal s1:

s0 <= 3
s1[3..0] <= i0 + i1

The behavior of a transmit statement depends on the execution mode of the enclosing block:

Control statements

There are only two possible control statements: the hardware if hif and the hardware case hcase.

hif

The hif construct is made of a condition and a block that is executed if and only if the condition is met. It is declared as follows, where the condition can be any expression:

hif <condition> do
   <block contents>
end

hcase

The hcase construct is made of an expression and a list of value-block pairs. A block is executed when the corresponding value is equal to the value of the expression of the hcase. This construct is declared as follows:

hcase <expression>
hwhen <value 0> do
   <block contents 0>
end
hwhen <value 1> do
   <block contents 1>
end
...

helse

It is possible to add a block that is executed when the condition of an hif is not met, or when no case matches the expression of a hcase, using the helse keyword as follows:

<hif or hcase construct>
helse do
   <block contents>
end

helsif

In addition to helse, it is possible to set additional conditions to an hif using the helsif keyword as follows:

hif <condition 0> do
   <block contents 0>
end
helsif <condition 1> do
   <block contents 1>
end
...

About loops

HDLRuby does not include any hardware construct for describing loops. This might look poor compared to the other HDL, but it is important to understand that the current synthesis tools do not synthesize hardware from such loops but instead preprocess them (e.g., unroll them) to synthesizable loopless hardware. In HDLRuby, such features are natively supported by the Ruby loop constructs (for, while, and so on), but also by advanced Ruby constructs like the enumerators (each, times, and so on).

Notes:

Types

Each signal and each expression is associated with a data type that describes the kind of value it can represent. In HDLRuby, the data types represent bit-vectors associated with the way they should be interpreted, i.e., as bit strings, unsigned values, signed values, or hierarchical contents.

Type Construction

There are five basic types, bit, signed, unsigned, integer, and float that represent respectively single bit logical values, single-bit unsigned values, single-bit signed values, Ruby integer values, and Ruby floating-point values (double precision). The first three types are HW and support four-valued logic, whereas the two last ones are SW (but are compatible with HW) and only support Boolean logic. Ruby integers can represent any element of Z (the mathematical integers) and have for that purpose a variable bit-width.

The other types are built from them using a combination of the two following type operators.

The vector operator [] is used for building types representing vectors of single or multiple other types. A vector whose elements have all the same type is declared as follows:

<type>[<range>]

The <range> of a vector type indicates the position of the starting and ending bits. An n..0 range can also be abbreviated to n+1. For instance, the two following types are identical:

bit[7..0]
bit[8]

A vector of multiple types, also called a tuple, is declared as follows:

[<type 0>, <type 1>, ... ]

For example, the following code declares the type of the vectors made of an 8-bit logical, a 16-bit signed, and a 16-bit unsigned values:

[ bit[8], signed[16], unsigned[16] ]

The structure operator {} is used for building hierarchical types made of named subtypes. This operator is used as follows:

{ <name 0>: <type 0>, <name 1>: <type 1>, ... }

For instance, the following code declares a hierarchical type with an 8-bit subtype named header and a 24-bit subtype named data:

{ bit[7..0], bit[23..0] }

Type definition

It is possible to give names to type constructs using the typedef keywords as follows:

<type construct>.typedef :<name>

For example, the following gives the name char to a signed 8-bit vector:

signed[7..0].typedef

After this statement, char can be used like any other type. For example, the following code sample declares a new input signal sig whose type is char:

char.input

Alternatively, a new type can also be defined using the following syntax:

typedef :<type name> do
   <code>
end

Where:

For example, the previous char could have been declared as follows:

typedef  do
   signed[7..0]
end

Type compatibility and conversion

The basis of all the types in HDLRuby is the vector of bits (bit vector) where each bit can have four values: 0, 1, Z, and X (for undefined). Bit vectors are by default unsigned but can be set to be signed. When performing computations between signals of different bit-vector types, the shorter signal is extended to the size of the larger one preserving its sign if it is signed.

While the underlying structure of any HDLRuby type is the bit vector, complex types can be defined. When using such types in computational expressions and assignments they are first implicitly converted to an unsigned bit vector of the same size.

Expressions

Expressions are any construct that represents a value associated with a type. They include immediate values, reference to signals and operations among other expressions using expression operators.

Immediate values

The immediate values of HDLRuby can represent vectors of bit, unsigned, and signed, and integer or floating-point numbers. They are prefixed by a _ character and include a header that indicates the vector type and the base used for representing the value, followed by a numeral representing the value. The bit width of a value is obtained by default from the width of the numeral, but it is also possible to specify it in the header. In addition, the character _ can be put anywhere in the number to increase the readability, but it will be ignored.

The vector type specifiers are the following:

The base specifiers are the following:

For example, all the following immediate values represent an 8-bit hundred (either in unsigned or signed representation):

_bb01100100
_b8b110_0100
_b01100100
_u8d100
_s8d100
_uh64
_s8o144

Finally, it is possible to omit either the type specifier, the default being unsigned bit, or the base specifier, the default being binary. For example, all the following immediate values represent an 8-bit unsigned hundred:

_b01100100
_h64
_o144

Notes:

References

References are expressions used to designate signals or a part of signals.

The simplest reference is simply the name of a signal. It designates the signal corresponding to this name in the current scope. For instance, in the following code, inner signal sig0 is declared, and therefore the name sig0 becomes a reference to designate this signal.

# Declaration of signal sig0.
inner 

# Access to signal sig0 using a name reference.
sig0 <= 0

For designating a signal of another system, or a sub-signal in a hierarchical signal, you can use the . operator as follows:

<parent name>.<signal name>

For example, in the following code, input signal d of system instance dff0 is connected to sub-signal sub0 of hierarchical signal sig.

system  do
   input , , 
   output 

   par(clk.posedge) { q <= d & ~rst }
end

system  do
   input , 
   { bit, bit}.inner 
   
   dff().(clk, rst)
   dff0.d <= sig.sub0
   ...
end

Expression operators

The following table gives a summary of the operators available in HDLRuby. More details are given for each group of operators in the subsequent sections.

Assignment operators (left-most operator of a statement):

      symbol       description              
:<= connection, if outside behavior
:<= transmission, if inside behavior

Arithmetic operators:

      symbol       description              
:+ addition
:- subtraction
:* multiplication
:/ division
:% modulo
:** power
:+@ positive sign
:-@ negation

Comparison operators:

      symbol       description              
:== equality
:!= difference
:> greater than
:< smaller than
:>= greater or equal
:<= smaller or equal

Logic and shift operators:

      symbol       description              
:& bitwise / logical and
:
:~ bitwise / logical not
:mux multiplex
:<< / :ls left shift
:>> / :rs right shift
:lr left rotate
:rr right rotate

Conversion operators:

      symbol       description              
:to_bit cast to bit vector
:to_unsigned cast to unsigned vector
:to_signed cast to signed vector
:to_big cast to big-endian
:to_little cast to little endian
:reverse reverse the bit order
:ljust increase width from the left, preserves the sign
:rjust increase width from the right, preserves the sign
:zext zero extension, converts to unsigned if signed
:sext sign extension, converts to sign

Selection /concatenation operators:

      symbol       description              
:[] sub-vector selection
:@[] concatenation operator
:. field selection

Notes:

Assignment operators

The assignment operators can be used with any type. They are the connection and the transmission operators both being represented by <=.

Note:

Arithmetic operators

The arithmetic operators can only be used on vectors of bit, unsigned or signed values, integer, or float values. These operators are +, -, *, % and the unary arithmetic operators are - and +. They have the same meaning as their Ruby equivalents.

Comparison operators

Comparison operators are the operators whose result is either true or false. In HDLRuby, true and false are represented by respectively bit value 1 and bit value 0. These operators are ==, !=, <, >, <=, >= . They have the same meaning as their Ruby equivalents.

Notes:

Logic and shift operators

In HDLRuby, the logic operators are all bitwise. For performing Boolean computations, it is necessary to use single-bit values. The bitwise logic binary operators are &, |, and ^, and the unary one is ~. They have the same meaning as their Ruby equivalents.

Note: there are two reasons why there are no Boolean operators

  1. Ruby language does not support the redefinition of the Boolean operators

  2. In Ruby, each value that is not false nor nil is assumed to be true. This is perfectly relevant for software, but not for hardware where the basic data types are bit vectors. Hence, it seemed preferable to support Boolean computation for one-bit values only, which can be done through bitwise operations.

The shift operators are << and >> and have the same meaning as their Ruby equivalent. They do not change the bit width and preserve the sign for signed values.

The rotation operators are rl and rr for respectively left and right bit rotations. Like the shifts, they do not change the bit width and preserve the sign for the signed values. However, since such operators do not exist in Ruby, they are used like methods as follows:

<expression>.rl(<other expression>)
<expression>.rr(<other expression>)

For example, for rotating the left signal sig 3 times, the following code can be used:

sig.rl(3)

It is possible to perform other kinds of shifts or rotations using the selection and concatenation operators. Please refer to section Concatenation and selection operators for more details about these operators.

Conversion operators

The conversion operators are used to change the type of an expression. There are two kinds of such operators: the type pun that does not change the raw value of the expression and the type cast that changes the raw value.

The type puns include to_bit, to_unsigned, and to_signed that convert expressions of any type to vectors of respectively bit, unsigned, and signed elements. For example, the following code converts an expression of hierarchical type to an 8-bit signed vector:

[ signed[3..0], unsigned[3..0] ].inner 
sig.to_bit <= _b01010011

The type casts change both the type and the value and are used to adjust the width of the types. They can only be applied to vectors of bit, signed, or unsigned and can only increase the bit width (bit width can be truncated using the selection operator, please refer to the next section). These operators comprise the bit width conversions: ljust, rjust, zext, and sext.

More precisely, the bit width conversions operate as follows:

Concatenation and selection operators

Concatenation and selection are done using the [] operator as follows:

Implicit conversions

When there is no ambiguity, HDLRuby will automatically insert conversion operators when two types are not compatible with one another. The cases where such implicit conversions are applied are summarized in the following tables, where:

Additive and logical operators:

operator result’s width
<= (assign) w (error is raised if L.width < R.width)
+, - w+1
&, |, ^ w
== 1
< 1
> 1
<= (comp.) 1
>= 1
S operand base L operand base result base operand conversion
bit bit bit S.zext(L.width)
bit unsigned unsigned S.zext(L.width).to_unsigned
bit signed signed S.zext(max(S.width+1,L.width).to_signed
unsigned bit unsigned S.zext(L.width), L.to_unsigned
unsigned unsigned unsigned S.zext(L.width)
unsigned signed signed S.zext(max(S.width+1,L.width).to_signed
signed bit signed S.sext(L.width+1), L.zext(L.width+1).to_signed
signed unsigned signed S.sext(L.width+1), L.zext(L.width+1).to_signed
signed signed signed S.sext(L.width)

Multiplicative operators:

operator result width
* lw * rw
/ lw
% rw
** rw
<< / ls lw
>> / rs lw
lr lw
rr lw
S operand base L operand base result base operand conversion
bit bit bit
bit unsigned unsigned S.to_unsigned
bit signed signed S.zext(S.width+1).to_signed
unsigned bit unsigned L.to_unsigned
unsigned unsigned unsigned
unsigned signed signed S.zext(S.width).to_signed
signed bit signed L.zext(L.width+1).to_signed
signed unsigned signed L.zext(L.width+1).to_signed
signed signed signed

Functions

HDLRuby functions

Like Verilog HDL, HDLRuby provides function constructs for reusing code. HDLRuby functions are declared as follows:

   hdef :<function name> do |<arguments>|
   <code>
   end

Where:

Notes:

A function can be invoked anywhere in the code using its name and passing its argument between parentheses as follows:

<function name>(<list of values>)

Ruby functions

HDLRuby functions are useful for reusing code, but they cannot interact with the code they are called in. For example, it is not possible to add interface signals through a function nor to modify a control statement (e.g., hif) with them. These high-level generic operations can however be performed using the functions of the Ruby language declared as follows:

def <function name>(<arguments>)
   <code>
end

Where:

These functions are called the same way HDLRuby functions are called, but this operation pastes the code of the function as is within the code. Moreover, these functions do not have any scope so any inner signal or instance declared within them will be added to the object they are invoked in.

For example, the following function will add input in0 to any system where it is invoked:

def add_in0
   input 
end

This function can be used as follows:

system  do
   ...
   add_in0
   ...
end

As another example, the following function will add an alternative code that generates a reset to a condition statement (hif or hcase):

def too_bad
   helse { rst <= 1 }
end

This function can be used as follows:

system  do
   ...
   par do
      hif(sig == 1) do
         ...
      end
      too_bad
   end
end

Ruby functions can be compared to the macros of the C languages: they are more flexible since they edit the code they are invoked in, but they are also dangerous to use. In general, it is not recommended to use them, unless when designing a library of generic code for HDLRuby.

Software code

It is possible to describe hardware-software components in HDLRuby using the program construct that encapsulates some software code a provides an interface for communicating with the hardware. This interface is composed of three kinds of components:

Note:

The same signal can be used at the same time by multiple ports for both reading and writing, however, from the software point of view, it will correspond to two different ports.

Declaring a software component

A software component is declared like a hardware process within a system. The syntax is the following:

program(<programming language>, <function name>) do
   <location of the software files and description of its interface>
end

In the code above, programming language is a symbol representing the programming language used for the software. For now, only two languages are supported:

The function name parameter indicates which function is to be executed when an activation event occurs. There can be only one such function per program, but any number of programs can be declared inside the same module.

The location of the software files and description of its interface part can include the following declaration statements:

For example the following declares a program in the Ruby language whose start function is echo that is activated on the positive edge of signal req, has a read port called inP that is connected to signal count and a write port called outP that is connected to signal val, finally the code of this program is given in a file named echo.rb:

system  do
   inner 
   [8].inner , 
 
   ...

   program(,'echo') do
      actport req.posedge
      inport   count
      outport val
      code "echo.rb"
   end
end

Note:

The size of the input and output ports is one of the signals they give access to. However, from the software side, their values are converted to long long types.

About the software code used in HDLRuby programs

Location and format of the files

The file names indicating the software code to use must indicate the path to these files relative to where the HDLRuby tools are used. In the example above, that would mean that the echo.rb program must be in the same directory as the HDLRuby description. If this code were to be into a ruby directory under the current directory, the declaration would become: code "ruby/echo.rb". For the Ruby language, any number of source files can be declared, and plain Ruby code can be used as is. However, for the C language, the software code must first be compiled, and it is the resulting file that must be declared in the code declaration. For example, if for the example above, C had to be used, then the program description would be the following:

   program(, ) do
      actport req.posedge
      inport   count
      outport val
      code "echo"
   end

Then, for this program to work, the C code must be compiled to a file named echo. Please notice that, in the example, the extension is omitted, to allow the system to look for the valid file type (e.g., .so for a Linux shared library).

Note:

The same software file can be used for several different program constructs, however the functions it contains will be unique for the whole device.

The hardware interface

From the software point of view, the hardware interface consists only of a list of ports that can either be read or written. However, the implementation of this interface depends on the language.

For Ruby

For ruby, the interface is accessed by requiring the rubyHDL library. It gives provides the RubyHDL module that provides accessors to ports of the program. For example, the following program reads on port inP and writes the results on port outP:

require 'rubyHDL'

def echo
   val = RubyHDL.inP
   RubyHDL.outP = val
end

Note:

As long as a port has been declared in the HDLRuby description of the program, it will be available to the software as a module accessor without the need for any additional declaration or configuration.

For C

For C (and C-compatible compiled languages), the interface is accessed by including the cHDL.h file. This file must be generated using the following command:

hdrcc --ch <destination project>

In the command above, <destination project> is the directory where the C code is meant to be.

Once generated, this file provides the three following C functions:

For example, the following program reads on port inP and writes the results on port outP:

#include "cHDL.h"

void echo() {
   void* inP = c_get_port("inP");
   void* outP = c_get_port("outP");
   int val;
   
   val = c_read_port(inP);
   c_write_port(outP,val);
}

Note:

#include "cHDL.h"

__declspec(dllexport) void echo() {
   void* inP = c_get_port("inP");
   void* outP = c_get_port("outP");
   int val;
   
   val = c_read_port(inP);
   c_write_port(outP,val);
}

Hardware-software co-simulation

As long as your programs a correctly described and the software files provided (and compiled in the case of C), the hardware-software co-simulation will be automatically performed when executing the HDLRuby simulator.

Compiling the C code

While programs in Ruby can be used directly, programs in C must be compiled first. For that purpose, the required files, including the hardware interface cHDL.h, must be generated. This is done by using the following HDLRruby command:

hdrcc --ch <destination project>

In the command above, <destination project> is both the directory where the C code is and the name of the resulting shared library.

For example, if you want to compile the code located in the directory echo you need first to execute:

hdrcc --ch echo

Then, you will have to put your C files into the resulting directory and go inside it for compiling. If you have some specific needs for this compiling, or if you do not want to rely on the Ruby environment, you can compile your program there as a shared library like any other project. For example, if you are using GCC, you could type (after entering the echo directory):

gcc -shared -fPIC -undefined dynamic_lookup  -o c_program.so echo.c

The command above is for compiling a single file project on a Linux system.

Otherwise, it may be easier to use the Ruby environment by first installing rake-compiler as follows:

gem install rake-compiler

And simply type the following command (after entering the echo directory):

rake compile

The rake tool will take care of everything for performing the compiling whatever your system may be.

Hardware generation

In the current stage, HDLRuby only generates the hardware part of a description. E.g., when generating Verilog, the programs are simply being ignored. It is therefore up to the user to provide additional code for implementing the hardware-software interface. The reason is that such interfaces are target-dependent, and often comprise licensed software and IP components that cannot be integrated into HDLruby.

This is less a limitation than it seems since it is possible to write program constructs that wrap such accesses so that the software and HDLRuby code can be used as is in the target system. As an illustration, you can consult the example given in the tutorial: 7.6. Hardware-software co-synthesis.

Extended co-simulation

Since HDLRuby programs can support any compiled software, these components can also be used for executing any kind of application that is not specifically meant to be executed on the target CPU. For instance, some peripheral circuits like a keyboard or a monitor can be modeled using an HDLRuby program, as illustrated in the HDLRuby sample with_program_ruby_cpu.rb.

Development board simulation graphical interface

HDLRuby provides a web browser-based GUI for the simulator as an extension of the co-design platform presented in this section. This GUI is to be declared as follows within a module:

board(:<board name>,<server port>) do
  actport <event>
  <description of the GUI>
end

In the code above, board name is the name of the board, server port is the local port the browser has to connect to for accessing the GUI (by default it is set to 8000), and event is the event (e.g., the rising edge of a clock) that activates the synchronization of the GUI with the simulator.

Then the description of the GUI consists of a list of the following possible development board-oriented elements. Active elements are to be given a name and attached to a HDLRuby signal as follows:

<element> <element name>: <HDLRuby signal>

The list of possible elements is as follows:

For example, for a GUI presenting an interface to an adder with input signals x and y and output signal z displayed as LEDs, a digit display, and an oscilloscope, the following description can be used:

system  do
  [8].inner , , 
  
  z <= x + y

  inner 
  
  board() do
    actport gui_sync.posedge
    sw x
    sw y
    row
    led z
    digit z
    row
    scope z
  end

  timed do
    clk <= 0
    repeat(10000) do
      !10.ns
      clk <= ~clk
    end
  end
end

With the code above, the GUI will show a row containing two sets of slide switches for input x and y, a row containing a set of LEDs and a digital display for showing z, and a row containing an oscilloscope for showing the evolution z.

This code is simulated exactly like any other HDLRuby description, e.g., the following command will start the simulation and generate a VCD wave file:

hdrcc --sim --vcd my_adder.rb my_adder

However, the simulator will wait until a browser connects to it. For that, you can open a web browser, and go to the local url: http://localhost:8000. The simulation will then start and you can interact with the GUI.

Time

Time values

In HDLRuby, time values can be created using the time operators: s for seconds, ms for a millisecond, us for microseconds, ns for nanoseconds, ps for picoseconds. For example, the following are all indicating one second:

1.s
1000.ms
1000000.us
1000000000.ns
1000000000000.ps

Time behaviors and time statements

Like the other HDL, HDLRuby provides specific statements that model the advance of time. These statements are not synthesizable and are used for simulating the environment of a hardware component. For the sake of clarity, such statements are only allowed in explicitly non-synthesizable behavior declared using the timed keyword as follows.

timed do
   <statements>
end

A time behavior does not have any sensitivity list, but it can include any statement supported by a standard behavior in addition to the time statements. There are two kinds of such statements:

Note:

This statement is not synthesizable and therefore can only be used in timed behaviors.

Parallel and sequential execution

Time behaviors are by default sequential, but they can include both parallel and sequential blocks. The execution semantic is the following:

High-level programming features

Using Ruby in HDLRuby

Since HDLRuby is pure Ruby code, the constructs of Ruby can be freely used without any compatibility issues. Moreover, this Ruby code will not interfere with the synthesizability of the design. It is then possible to define Ruby classes, methods, or modules whose execution generates constructs of HDLRuby.

Generic programming

Declaring

Declaring generic systems

Systems can be declared with generic parameters as follows:

system :<system name> do |<list of generic parameters>|
   ...
end

For example, the following code describes an empty system with two generic parameters named respectively a and b:

system() { |a,b| }

The generic parameters can be anything: values, data types, signals, systems, Ruby variables, and so on. For example, the following system uses generic argument t as a type for an input signal, generic argument w as a bit range for an output signal, and generic argument s as a system used for creating instance sI whose input and output signals i and o are connected respectively to signals isig and osig.

system  do |t,w,s|
   t.input isig
   [w].output osig

   s .(isig, osig)
end

It is also possible to use a variable number of generic parameters using the variadic operator * like in the following example. In this example, args is an array containing an indefinite number of parameters.

system() { |*args| }
Declaring generic types

Data types can be declared with generic parameters as follows:

typedef :<type name> do |<list of generic parameters>|
   ...
end

For example, the following code describes a bit-vector type with a generic number of bits width:

type() { |width| bit[width] }

Like with the systems, the generic parameters of types can be any kind of object, and it is also possible to use variadic arguments.

Specializing

Specializing generic systems

A generic system is specialized by invoking its name and passing as an argument the values corresponding to the generic arguments as follows:

<system name>(<generic argument value's list>)

If fewer values are provided than the number of generic arguments, the system is partially specialized. However, only a fully specialized system can be instantiated.

A specialized system can also be used for inheritance. For example, assuming system sys has 2 generic arguments, it can be specialized and used for building system subsys as follows:

system , sys(1,2) do
   ...
end

This way of inheriting can only be done with fully specialized systems though. For partially specialized systems, include must be used instead. For example, if sys is specialized with only one value, can be used in generic subsys_gen as follows:

system  do |param|
   include sys(1,param)
   ...
end

Note:

Specializing generic types

A generic type is specialized by invoking its name and passing as an argument the values corresponding to the generic arguments as follows:

<type name>(<generic argument value's list>)

If fewer values are provided than the number of generic arguments, the type is partially specialized. However, only a fully specialized type can be used for declaring signals.

Use of signals as generic parameters

Signals passed as generic arguments to systems can be used for making generic connections to the instance of the system. For that purpose, the generic argument has to be declared as input, output, or inout port in the body of the system as follows:

system :<system_name> do |sig|
   sig.input 
   ...
end

In the code above, sig is a generic argument assumed to be a signal. The second line declares the port to which sig will be connected to when instantiating. From there, port my_sig can be used like any other port of the system. Such a system is then instantiated as follows:

system_name(some_sig) :<instance_name>

In the code above, some_sig is a signal available in the current context. This instantiation automatically connects some_sig to the instance.

Inheritance

Basics

In HDLRuby, a system can inherit from the content of one or several other parent systems using the include command as follows: include <list of systems>. Such an include can be put anywhere in the body of a system, but the resulting content will be accessible only after this command.

For example, the following code describes first a simple D-FF, and then uses it to describe a FF with an additional reversed output (qb):

system  do
   input , , 
   output 

   par(clk.posedge) { q <= d & ~rst }
end

system  do
    output 

    include dff

    qb <= ~q
end

It is also possible to declare inheritance in a more object-oriented fashion by listing the parents of a system just after declaring its name as follows:

system :<new system name>, <list of parent systems> do
   <additional system code>
end

For example, the following code is another to describe dff_full:

system , dff do
   output 

   qb <= ~q
end

Note:

About inner signals and system instances

By default, inner signals and instances of a parent system are not accessible by its child systems. They can be made accessible using the export keyword as follows: export <symbol 0>, <symbol 1>, .... For example, the following code exports signals clk and rst and instance dff0 of system exporter so that they can be accessed in child system importer.

system  do
   input 
   inner , 

   dff().(clk, rst, d)

   export , ,  
end

system , exporter do
   input , 
   output 

   clk <= clk0
   rst <= rst0
   dff0.q <= q
end

Note: - export takes as arguments the symbols (or the strings) representing the name of the components to export and not a reference to them. For instance, the following code is invalid:

system  do
   input 
   inner , 

   dff().(clk, rst, d)

   export clk, rst, dff0 
end

Conflicts when inheriting

Signals and instances cannot be overridden, this is also the case for signals and instances accessible through inheritance. For example, the following code is invalid since rst has already been defined in dff:

   system , dff do
      input 
   end

Conflicts among several inherited systems can be avoided by renaming the signals and instances that collide with one another as shown in the next section.

Shadowed signals and instances

It is possible in HDLRuby to declare a signal or an instance whose name is identical to the one used in one of the included systems. In such a case, the corresponding construct of the included system is still present, but it is not directly accessible even if exported, they are said to be shadowed.

To access the shadowed signals or instances, a system must be reinterpreted as the relevant parent system using the as operator as follows: as(system).

For example, in the following code signal, db of system dff_db is shadowed by signal db of system dff_shadow, but it is accessed using the as operator.

system  do
   input ,,
   inner 
   output 

   db <= ~d
   (q <= d & ~rst).at(clk.posedge)
end

system , dff_db do
   output , 

   db <= ~d
   qb <= as(dff_db).db
end

Opening a system

It is possible to pursue the definition of a system after it has been declared using the open methods as follows:

<system>.open do
   <additional system description>
end

For example, dff, a system describing a D-FF, can be modified to have an inverted output as follows:

dff.open do
   output 

   qb <= ~q
end

Opening an instance

When there is a modification to apply to an instance, it is sometimes preferable to modify this sole instance rather than declaring a new system to derivate the instance from. For that purpose, it is possible to open an instance for modification as follows:

<instance name>.open do
   <additional description for the instance>
end

For example, an instance of the previous dff system can be extended with an inverted output as follows:

system  do
   ...
   dff 
   dff0.open do
      output 
      qb <= ~q
   end
   ...
end

Overloading of operators

Operators can be overloaded for specific types. This allows for instance to support seamlessly fixed-point computations without requiring explicit readjustment of the position of the decimal point.

An operator is redefined as follows:

<type>.define_operator(:<op>) do |<args>|
   <operation description>
end

Where:

For example, for fix32 a 32-bit (decimal point at 16-bit) fixed-point type defined as follows:

signed[31..0].typedef()

The multiplication operator can be overloaded as follows to ensure the decimal point have always the right position:

fix32.define_operator(:*) do |left,right|
   (left.as(signed[31..0]) * right) >> 16
end

Please notice, that in the code above, the left value has been cast to a plain bit-vector to avoid the infinite recursive call of the * operator.

Operators can also be overloaded with generic types. However, in such a case, the generic argument must also be present in the list of arguments of the overloaded operators. For instance, let us consider the following fixed-point type of variable width (whose decimal point is set at half of its bit range):

typedef() do |width|
   signed[(width-1)..0]
end

The multiplication operator would be overloaded as follows:

fixed.define_operator do |width,left,right|
   (left.as(signed[(width-1)..0]) * right) >> width/2
end

Predicate and access methods

To get information about the current state of the hardware description HDLRuby provides the following predicates:

predicate name predicate type predicate meaning
is_block? bit tells if in execution block
is_par? bit tells if current parallel block is parallel
is_seq? bit tells if current parallel block is sequential
is_clocked? bit tells if current behavior is clocked (activated on a sole rising or falling edge of a signal)
cur_block block gets the current block
cur_behavior behavior gets the current behavior
cur_systemT system gets the current system
top_block block gets the top block of the current behavior
one_up block/system gets the upper construct (block or system)
last_one any last declared construct

Several enumerators are also provided for accessing the internals of the current construct (in the current state):

enumerator name accessed elements
each_input input signals of the current system
each_output output signals of the current system
each_inout inout signals of the current system
each_behavior behaviors of the current system
each_event events of the current behavior
each_block blocks of the current behavior
each_statement statements of the current block
each_inner inner signals of the current block (or system if not within a block)

Defining and executing Ruby methods within HDLRuby constructs

Like with any Ruby program, it is possible to define and execute methods anywhere in HDLRuby using the standard Ruby syntax. When defined, a method is attached to the enclosing HDLRuby construct. For instance, when defining a method when declaring a system, it can be used within this system only, while when defining a method outside any construct, it can be used everywhere in the HDLRuby description.

A method can include HDLRuby code in which case the resulting hardware is appended to the current construct. For example, the following code adds a connection between sig0 and sig1 in the system sys0, and transmission between sig0 and sig1 in the behavior of sys1.

def some_arrow
   sig1 <= sig0
end

system  do
   input 
   output 

   some_arrow
end

system  do
   input , 
   output 

   par(clk.posedge) do
      some_arrow
   end
end

Warning:

Like any other Ruby method, methods defined in HDLRuby support variadic arguments named arguments, and block arguments. For example, the following method can be used to connect a driver to multiple signals:

def mconnect(driver, *signals)
   signals.each do |signal|
      signal <= driver
   end
end

system  do
   input 
   input , , , 

   mconnect(i0,o0,o1,o2,o3)
end

While requiring caution, a properly designed method can be very useful for clean code reuse. For example, the following method allows to start the execution of a block after a given number of cycles:

def after(cycles, rst, &code)
   sub do
      inner 
      hif rst == 1 do
         count <= 0
      end
      helse do
         hif count < cycles do
            count <= count + 1
         end
         helse do
            instance_eval(&code)
         end
      end
   end
end

In the code above:

The following is an example that switches an LED on after 1000000 clock cycles using the previously defined after ruby method:

system  do
   output 
   input , 

   par(clk.posedge) do
      (led <= 0).hif(rst)
      after(100000,rst) { led <= 1 }
   end
end

Note:

Extending HDLRuby

Like any Ruby class, the constructs of HDLRuby can be dynamically extended. If it is not recommended to change their internal structure, it is possible to add methods to them for an extension.

Extending HDLRuby constructs globally

By global extension of hardware constructs, we mean the classical extension of Ruby classes by monkey patching the corresponding class. For example, it is possible to add a method giving the number of signals in the interface of a system instance as follows:

class SystemI
   def interface_size
      return each_input.size + each_output.size + each_inout.size
   end
end

From there, the method interface_size can be used on any system instance as follows: <system instance>.interface_size.

The following table gives the class of each construct of HDLRuby.

construct class
data type Type
system SystemT
scope Scope
system instance SystemI
signal Signal
connection Connection
par/seq Behavior
timed TimeBehavior
event Event
par/seq/sub Block
transmit Transmit
hif If
hcase Case
program Program

Extending HDLRuby constructs locally

By local extension of a hardware construct, we mean that while the construct will be changed, all the other constructs will remain unchanged. This is achieved like with Ruby by accessing the Eigen class using the singleton_class method and extending it using the class_eval method. For example, with the following code, only system dff will respond to method interface_size:

dff.singleton_class.class_eval do
   def interface_size
      return each_input.size + each_output.size + each_inout.size
   end
end

It is also possible to extend locally an instance using the same methods. For example, with the following code, only instance dff0 will respond to method interface_size:

dff 

dff0.singleton_class.class_eval do
   def interface_size
      return each_input.size + each_output.size + each_inout.size
   end
end

Finally, it is possible to extend locally all the instances of a system using method singleton_instance in place of method singleton_class. For example, with the following code, all the instances of system dff will respond to method interface_size:

dff.singleton_instance.class_eval do
   def interface_size
      return each_input.size + each_output.size + each_inout.size
   end
end

Modifying the generation behavior

The main purpose of allowing global and local extensions for hardware constructs is to give the user the possibility to implement its synthesis methods. For example, one may want to implement some algorithm for a given kind of system. For that purpose, the user can define an abstract system (without any hardware content), that holds the specific algorithm as follows:

system() {}

my_base.singleton_instance.class_eval do
   def my_generation
      <some code>
   end
end

Then, when this system named my_base is included in another system, this latter will inherit from the algorithms implemented inside method my_generation as shown in the following code:

system , my_base do
   <some system description>
end

However, when generation the low-level description of this system, code like the following will have to be written for applying my_generation:

some_system 
instance0.my_generation
low = instance0.to_low

This can be avoided by redefining the to_low method as follows:

system() {}

my_base.singleton_instance.class_eval do
   def my_generation
      <some code>
   end

   alias  
   def to_low
      my_generation
      _to_low
   end
end

This way, calling directly to_low will automatically use my_generation.

Standard libraries

The standard libraries are included in the module Std. They can be loaded as follows, where <library name> is the name of the library:

require 'std/<library name>'

After the libraries are loaded, the module Std must be included as follows:

include HDLRuby::High::Std

However, hdrcc loads the stable components of the standard library by default, so you do not need to require nor include anything more to use them. In the current version, the stable components are the following:

Clocks: std/clocks.rb

The clocks library provides utilities for easier handling of clock synchronizations.

It adds the possibility to multiply events by an integer. The result is a new event whose frequency is divided by the integer multiplicand. For example, the following code describes a D-FF that memorizes each three clock cycles.

require 'std/clocks'
include HDLRuby::High::Std

system  do
   input , 
   input 
   output 

   ( q <= d & ~rst ).at(clk.posedge * 3)
end

Note: this library generates all the RTL code for the circuit handling the frequency division.

Counters: std/counters.rb

This library provides two new constructs for implementing synthesizable wait statements.

The first construct is the after statement that activates a block after a given number of clock cycles is passed. Its syntax is the following:

after(<number>,<clock>,<reset>)

Where:

This statement can be used inside a clocked behavior where the clock event of the behavior is used for the counter unless specified otherwise.

The second construct is the before statement that activates a block until a given number of clock cycles is passed. Its syntax and usage are identical to the after statement.

Decoder: std/decoder.rb

This library provides a new set of control statements for easily describing an instruction decoder.

A decoder can be declared anywhere in the code describing a system using the decoder keyword as follows:

decoder(<signal>) <block>

Where signal is the signal to decode and block is a procedure block (i.e., Ruby proc) describing the decoding procedure. This procedure block can contain any code supported by a standard behavior but also supports the entry statement that describes a pattern of a bit vector to decode and the corresponding action to perform when the signal matches this pattern. The syntax of the entry statement is the following:

entry(<pattern>) <block>

Where pattern is a string describing the pattern to match the entry, and block is a procedure block describing the actions (some HDLRuby code) that are performed when the entry matches. The string describing the pattern can include 0 and 1 characters for specifying a specific value for the corresponding bit, or any alphabetical character for specifying a field in the pattern. The fields in the pattern can then be used by name in the block describing the action. When a letter is used several times within a pattern, the corresponding bits are concatenated and used as a multi-bit signal in the block.

For example, the following code describes a decoder for signal ir with two entries, the first one computing the sum of fields x and y and assigning the result to signal s and the second one computing the sum of fields x y and z and assigning the result to signal s:

decoder(ir) do
   entry("000xx0yy") { s <= x + y }
   entry("10zxxzyy") { s <= x + y + z }
end

It can be noticed for field z in the example above that the bits are not required to be contiguous.

FSM: std/fsm.rb

This library provides a new set of control statements for easily describing a finite state machine (FSM).

A finite state machine can be declared anywhere in a system provided it is outside a behavior using the fsm keyword as follows:

fsm(<event>,<reset>,<mode>) <block>

Where event is the event (rising or falling edge of a signal) activating the state transitions, rst is the reset signal, mode is the default execution mode, and block is the execution block describing the states of the FSM. This last parameter can be either :sync for synchronous (Moore type) or :async for asynchronous (Mealy type).

The states of an FSM are described as follows:

<kind>(<name>) <block>

Where kind is the kind of state, name is the name of the state, and block is the actions to execute for the corresponding state. The kinds of states are the following:

In addition, it is possible to define a default action that will be executed whatever the state is using the following statement:

default <block>

Where block is the action to execute.

State transitions are by default set to be from one state to the following in the description order. If no more transition is declared the next one is the first declared transition. A specific transition is defined using the goto statement as the last statement of the action block as follows:

goto(<condition>,<names>)

Where condition is a signal whose value is used as an index for selecting the target state among the ones specified in the names list. For example, the following statement indicates to go to the state named st_a if the cond is 0, st_b if the condition is 1, and st_c if the condition is 2, otherwise this specific transition is ignored:

goto(cond,,,)

Several goto statements can be used, the last one having priority provided it is taken (i.e., its condition corresponds to one of the target states). If no goto is taken, the next transition is the next declared one.

For example, the following code describes an FSM describing a circuit that checks if two buttons (but_a and but_b) are pressed and released in sequence for activating an output signal (ok):

fsm(clk.posedge,rst,) do
   default { ok <= 0 }
   reset do
      goto(but_a, , but_a_on)
   end
   state() do
      goto(but_a, , )
   end
   state() do
      goto(but_b, , )
   end
   state() do
      goto(but_b, , )
   end
   state() do
      ok <= 1
      goto()
   end
end

Note: the goto statements act globally, i.e., they are independent of the place where they are declared within the state. For example for both following statements, the next state will always be st_a whatever cond may be:

   state() do
      goto()
   end
   state() do
      hif(cond) { goto() }
   end

That is to say, for a conditional goto for st_1 the code should have been written as follows:

   state() do
      goto(cond,)
   end

The use of goto makes the design of FSM shorter for a majority of the cases, be sometimes, a finer control is required. For that purpose, it is also possible to configure the FSM in static mode where the next_state statement indicates implicitly the next state. Putting in static mode is done by passing :static as an argument when declaring the FSM. For example, the following FSM uses next_state to specify explicitly the next states depending on some condition signals cond0 and cond1:

fsm(clk.posedge,rst,)
   state() do
      next_state()
   state() do
      hif(cond) { next_state() }
      helse { next_state() }
   end
end

Sequencer (software-like hardware coding):: std/sequencer.rb

This library provides a new set of control statements for describing the behavior of a circuit. Behind the curtain, these constructs build a finite state machine where states are deduced from the control points within the description.

A sequencer can be declared anywhere in a system provided it is outside a behavior using the sequencer keyword as follows:

sequencer(<clock>,<start>) <block>

Where clock is the clock signal advancing the execution of the sequence, start is the signal starting the execution, and block is the description of the sequence to be executed. Both clock and start can also be events (i.e., posedge or negedge).

A sequence is a specific case of a seq block that includes the following software-like additional constructs:

It is also possible to use enumerators (iterators) similar to the Ruby each using the following methods within sequences:

The objects that support these methods are called enumerable objects. They include the HDLRuby signals, the HDLRuby enumerators, and all the Ruby enumerable objects (e.g., ranges, arrays).

Here are a few examples of sequencers synchronized in the positive edge of clk and starting when start becomes one. The first one computes the Fibonacci series until 100, producing a new term in signal v at each cycle:

require 'std/sequencer.rb'
include HDLRuby::High::Std

system  do
   inner , 
   [16].inner , 
   
   sequencer(clk.posedge,start) do
      a <= 0
      b <= 1
      swhile(v < 100) do
         b <= a + b
         a <= b - a
      end
   end
end

The second one computes the square of the integers from 10 to 100, producing one result per cycle in signal a:

inner , 
[16].inner 

sequencer(clk.posedge,start) do
   10.supto(100) { |i| a <= i*i }
end

The third one reverses the content of memory mem (the result will be “!dlrow olleH”):

inner , 
bit[8][-12].inner "Hello world!"

sequencer(clk.posedge,start) do
   mem.size.stimes do |i|
      [8].inner 
      tmp       <= mem[i]
      mem[i]    <= mem[-i-1]
      mem[-i-1] <= tmp
   end
end

The fourth one computes the sum of all the elements of memory mem but stops if the sum is larger than 16:

inner , 
bit[8][-8].inner [ _h02, _h04, _h06, _h08, _h0A, _h0C, _h0E ]
bit[8] 

sequencer(clk.posedge,start) do
   sum <= 0
   sfor(mem) do |elem|
      sum <= sum + elem
      sif(sum > 16) { sterminate }
   end
end

HDLRuby enumerators and enumerable objects: std/sequencer.rb

HDLRuby enumerators are objects for generating iterations within sequencers. They are created using the method seach on enumerable objects as presented in the previous section.

The enumerators can be controlled using the following methods:

It is also possible to define a custom enumerator using the following command:

<enum> = senumerator(<typ>,<size>) <block>

Where enum is a Ruby variable referring to the enumerator, typ is the data type, size is the number of the elements to enumerate, and block is the block that implements the access to an element by index. For example, an enumerator on a memory could be defined as follows:

    bit[8][-8].inner [ _h01, _h02, _h03, _h04, _h30, _h30, _h30, _h30 ]
    [3].inner 
    [8].inner 

    data <= mem[addr]

    mem_enum = senumerator(bit[8],8) do |i|
        addr <= i
        step
        data
    end

In the code above, mem_enum is the variable referring to the resulting enumerator built for accessing memory mem. For the access, it is assumed that one cycle must be waited for after the address is set, and therefore a step command is added in the access procedure before data can be returned.

With this basis, several algorithms have been implemented using enumerators and are usable for all the enumerable objects. All these algorithms are HW implantation of the Ruby Enumerable methods. They are accessible using the corresponding ruby method prefixed by character s. For example, the HW implementation of the ruby all? method is generated by the sall? method. In details:

Shared signals, arbiters, and monitors: std/sequencer_sync.rb

Shared signals

Like any other process, several sequencers can’t write to the same signal. This is because there would be race competition that may physically destroy the device if such operations were authorized. In standard RTL design, this limitation is overcome by implementing three-state buses, multiplexers, and arbiters. However, HDLRuby sequencers support another kind of signal called the shared signals that abstract the implementation details for avoiding race competition.

The shared signals are declared like the other kind of signals from their type. The syntax is the following:

<type>.shared <list of names>

They can also have an initial (and default) value when declared as follows:

<type>.shared <list of names with initialization>

For example, the following code declares two 8-bit shared signals x and y, and two signed 16-bit shared signals initialized to 0 u and v:

[8].shared , 
signed[8].shared 0, 0

A shared signal can then be read and written to by any sequencer from anywhere in the subsequent code of the current scope. However, they cannot be written outside a sequencer. For example, the following code is valid:

input , 
[8].inner , 
[8].shared , 

val0 <= x+y
par(clk.posedge) { val1 <= x+y }

sequencer(clk.posedge,start) do
   10.stimes { |i| x <= i }
end

sequencer(clk.posedge,start) do
   5.stimes { |i| x <= i*2 ; y <= i*2 }
end

But the following code is not valid:

[8].shared 0

par(clk.posedge) { w <= w + 1 }

By default, a shared signal acknowledges writing from the first sequencer that accesses it in order of declaration, the others are ignored. In the first example given above, that means for signal x the value is always the one written by the first sequencer, i.e., from 0 to 9 changing once per clock cycle. However, the value of signal y is set by the second sequencer since it is this one only that writes to this signal.

This default behavior of shared signal avoids race competition but is not very useful in practice. For better control, it is possible to select which sequencer is to be acknowledged for writing. This is done by setting the number of the sequencer which can write the signal that controls the sharing accessed as follows:

<shared signal>.select

The select value starts from 0 for the first sequencer writing to the shared signal and is increased by one per writing sequencer. For example, in the first example, for selecting the second sequencer for writing to x the following code can be added after this signal is declared:

   x.select <= 1

This value can be changed at runtime too. For example, instead of setting the second sequencer, it is possible to switch the sequencer every clock cycle as follows:

   par(clk.posedge) { x.select <= x.select + 1 }

Note: this select sub-signal is a standard RTL signal that has the same properties and limitations as the other ones, i.e., this is not a shared signal itself.

Arbiters

Usually, it is not the signals that we want to share, but the resources they drive. For example, with a CPU, it is the ALU that is shared as a whole rather than each of its inputs separately. To support such cases and ease the handling of shared signals, the library also provides the arbiter components. This component is instantiated like a standard module as follows, where name is the name of the arbiter instance:

arbiter(:<name>).(<list of shared signal>)

When instantiated, an arbiter will take control of the select sub-signals of the shared signals (hence, you cannot control the selection yourself for them any longer). In return, it provides the possibility of requiring or releasing access to the shared signals. Requiring access is done by sending the value 1 to the arbiter, and releasing is done by sending the value 0. If a sequencer writes to a shared signal under arbitration without requiring access first, the write will simply be ignored.

The following is an example of an arbiter that controls access to shared signals x and y and two sequencers acquiring and releasing accesses to them:

input , 
[8].shared x, y
arbiter().(x,y)

sequencer(clk.posedge,start) do
   ctrl_xy <= 1
   x <= 0 ; y <= 0
   5.stime do |i|
      x <= x + 1
      y <= y + 2
   end
   ctrl_xy <= 0
end

sequencer(clk.posedge,start) do
   ctrl_xy <= 1
   x <= 2; y <= 1
   10.stime do |i|
      x <= x + 2
      y <= y + 1
   end
   ctrl_xy <= 0
end

In the example, both sequencers require access to signals x and y before accessing them and then releasing the access.

Requiring access does not guarantee that the access will be granted by the arbiter though. In the access is not granted, the write access will be ignored. The default access granting policy of an arbiter is the priority in the order of sequencer declaration. I.e., if several sequencers are requiring one at the same time, then the one declared the earliest in the code gains write access. For example, with the code given above, the first sequencer has to write access to x and y, and since after five write cycles it releases access, the second sequencer can then write to these signals. However, not obtaining write access does not block the execution of the sequencer, simply, its write access to the corresponding shared signals is ignored. In the example, the second sequencer will do its first five loop cycles without any effect and have only its five last ones that change the shared signals. To avoid such a behavior, it is possible to check if the write access is granted using arbiter sub signal acquired: if this signal is one in the current sequencer, that means the access is granted, otherwise it is 0. For example the following will increase signal x only if write access is granted:

hif(ctrl_xy.acquired) { x <= x + 1 }

The policy of an arbiter can be changed using command policy. You can either provide a new priority table, containing the number of the sequencers in order of priority (the first one having higher priority. The number of a sequencer is assigned in order of declaration provided it uses the arbiter. For example, in the previous code, the second sequencer can be given higher priority by adding the following code after having declared the arbiter:

ctrl_xy.policy([1,0])

It is also possible to set a more complex policy by providing to the policy method a block of code whose argument is a vector indicating which sequencer is currently requiring write access to the shared signals and whose result will be the number of the sequencer to grant the access. This code will be executed each time write access is performed. For example, in the previous code, a policy switch priorities at each access can be implemented as follows:

inner 0
inner grant_xy
ctrl_xy.policy do |acq|
   hcase(acq)
   hwhen(_b01) do
      grant_xy <= 0
      priority_xy <= ~priority_xy
   end
   hwhen(_b10) do
      grant_xy <= 1
      priority_xy <= ~priority_xy
   end
   hwhen(_b11) do
      grant_xy <= priority_xy
      priority_xy <= ~priority_xy
   end
   grant_xy
end

As seen in the code above, each bit of the acq vector is one when the corresponding sequencer requires access or 0 otherwise, bit 0 corresponds to sequencer 0, bit 1 to sequencer 1, and so on.

Monitors

Arbiters are especially useful when we can ensure that the sequencers accessing the same resource do not overlap or when they do not need to synchronize with each other. If such synchronizations are required, instead of arbiters, it is possible to use the monitor components.

The monitor component is instantiated like the arbiters as follows:

monitor(:<name>).(<list of shared signals>)

Monitors are used the same ways as arbiters (including the write access granting policies) but block the execution of the sequencers that require write access until the access is granted. If we take the example of code with two sequencers given as an illustration of arbiter usage, replacing the arbiter with a monitor as follows will lock the second sequencer until it can write to shared variables x and y ensuring that all its loop cycles have the specified result:

monitor().(x,y)

Since monitors lock processes, they automatically insert a step. Hence to avoid confusion, acquiring access to a monitor is done by using the method lock instead of assigning 1, and releasing is done by using the method unlock instead of assigning 0. Hence, when using a monitor, the previous arbiter-based code should be rewritten as follows:

input , 
[8].shared x, y
monitor().(x,y)

sequencer(clk.posedge,start) do
   ctrl_xy.lock
   x <= 0 ; y <= 0
   5.stime do |i|
      x <= x + 1
      y <= y + 2
   end
   ctrl_xy.unlock
end

sequencer(clk.posedge,start) do
   ctrl_xy.lock
   x <= 2; y <= 1
   10.stime do |i|
      x <= x + 2
      y <= y + 1
   end
   ctrl_xy.unlock
end

Sequencer-specific function: std/sequencer_func.rb

HDLRuby function defined by hdef can be used in a sequencer like any other HDLRuyby construct. But like the process constructs hif and so on, the body of these functions cannot include any sequencer-specific constructs.

However, it is possible to define functions that do support the sequencer constructs using sdef instead of hdef as follows:

   sdef :<function name> do |<arguments>|
   <sequencer code>
   end

Such functions can be defined anywhere in a HDLRuby description, but can only be called within a sequencer.

As additional features, since the sdef function is made to support the software-like code description of the sequencers, it also supports recursion. For example, a function describing a factorial can be described as follows:

sdef() do |n|
    sif(n > 1) { sreturn(n*fact(n-1)) }
    selse      { sreturn(1) }
end

As seen in the code above, a new construct sreturn can be used for returning a value from anywhere inside the function.

When a recursion is present, HDLRuby automatically defines a stack for storing the return state and the arguments of the function. The size of the stack is heuristically set to the maximum number of bits of the arguments of the function when it is recursively called. For example, for the previous fact function, if when called, n is 16-bit, the stack will be able to hold 16 recursions. If this heuristic does not match the circuit’s needs, the size can be forced as a second argument when defining the function. For example, the following code sets the size to 32 whatever the arguments are:

sdef(,32) do |n|
    sif(n > 1) { sreturn(n*fact(n-1)) }
    selse      { sreturn(1) }
end

Notes:

Fixed-point (fixpoint): std/fixpoint.rb

This library provides a new fixed point set of data types. These new data types can be bit vectors, unsigned or signed values and are declared respectively as follows:

bit[<integer part range>,<fractional part range>]
unsigned[<integer part range>,<fractional part range>]
signed[<integer part range>,<fractional part range>]

For example, a signed 4-bit integer part 4-bit fractional part fixed point inner signal named sig can be declared as follows:

bit[4,4].inner

When performing computation with fixed-point types, HDLRuby ensures that the result’s decimal point position is correct.

In addition to the fixed point data type, a method is added to the literal objects (Numeric) to convert them to fixed-point representation:

<litteral>.to_fix(<number of bits after the decimal point>)

For example, the following code converts a floating-point value to a fixed-point value with 16 bits after the decimal point:

3.178.to_fix(16)

Channel: std/channel.rb

This library provides a unified interface to complex communication protocols through a new kind of component called the channels that abstract the details of communication protocols. The channels can be used similarly to the ports of a system and are used through a unified interface so that changing the kind of channel, i.e., the communication protocol, does not require any modification of the code.

Using a channel

A channel is used similarly to a pipe: it has an input where data can be written and an output where data can be read. The ordering of the data and the synchronization depend on the internals of the channel, e.g., a channel can be FIFO or LIFO. The interaction with the channel is done using the following methods:

For example, a system sending successive 8-bit values through a channel can be described as follows:

system  do |channel|
    # Inputs of the producer: clock and reset.
    input , 
    # Inner 8-bit counter for generating values.
    [8].inner 

    # The value production process
    par(clk.posedge) do
        hif(rst) { counter <= 0 }
        helse do
            channel.write(counter) { counter <= counter + 1 }
        end
    end
end

Note: In the code above, the channel is passed as a generic argument of the system.

The access points to a channel can also be handled individually by declaring ports using the following methods:

Such a port can then be accessed using the same read and write method of a channel, the difference being that they can also be configured for new access procedures using the wrap method:

For example, assuming mem is a channel whose read and write access have as argument the target address and data signals, the following code creates a port for always accessing at address 0:

  addr0 = channel.input.wrap(0)

Channel branches

Some channels may include several branches, they are accessed by name using the following method:

A branch is a full-fledged channel and is used identically. For instance, the following code gets access to branch number 0 of channel ch, gets its inputs port, reads it, and put the result in signal val on the rising edges of signal clk:

br = ch.branch(0)
br.input
par(clk.posedge) { br.read(val) }

Declaring a channel

A new channel is declared using the keyword channel as follows:

channel <name> <block>

Where name is the name of the channel and block is a procedure block describing the channel. This block can contain any HDLRuby code, and is comparable to the content of a block describing a system with the difference that it does not have standard input, output, and inout ports are declared differently, and that it supports the following additional keywords:

For example, a channel implemented by a simple register of generic type typ, that can be set to 0 using the reset command can be described as follows:

channel  do |typ|
   # The register.
   typ.inner 

   # The reader procedure can read reg
   reader_input 
   # The writer procedure can write reg
   writer_output 

   # Declares a reset
   command() { reg <= 0 }

   # Defines the reader procedure.
   reader do |blk,target|
      target <= reg
      blk.call if blk
   end

   # Defines the writer procedure.
   writer do |blk,target|
      reg <= target
      blk.call if blk
   end
end

Notes:

Like systems, a channel must be instantiated for being used, and the instantiation procedure is identical:

<channel name> :<instance name>

And in case there is a generic parameter, the instantiation procedure is as follows:

<channel name>(:<instance name>).(<generic parameters>)

After a channel is instantiated, it must be linked to the circuits that will communicate through it. This is done when instantiating these circuits. If a circuit reads or writes on the channel, it will be instantiated as follows:

<system name>(<channel instance>).(:<instance name>).(<circuit standard connections>)

Notes:

The following code is an example instantiating the register channel presented above for connecting an instance of producer8 and another circuit called consumer8:

# System wrapping the producer and the consumer circuits.
system  do
   # The clock and reset of the circuits
   input , 

   # Instance of the channel (using 8-bit data).
   regch([8]).()

   # Reset the channel on positive edges of signal rst.
   regchI.reset.at(rst.posedge)

   # Instantiate the producer.
   producer8(regch).().(clk,rst)

   # Instantiate the consumer.
   consumer8(regch).().(clk.rst)
end

Note:

Sample HDLRuby descriptions

Several samples HDLRuby descriptions are available in the following directory:

path/to/HDLRuby/lib/HDLRuby/hdr_samples

For the gem install, the path to HDLRuby can be found using the following:

gem which HDLRuby

But you can also import the samples to your local directory with the following command (recommended):

hdrcc --get-samples

The naming convention of the samples is the following:

Contributing

Bug reports and pull requests are welcome on GitHub at https://github.com/civol/HDLRuby.

To do

License

The gem is available as open-source under the terms of the MIT License.